1. Field of the Invention
The present invention generally relates to the phase locking of signals, and more particularly relates to the phase alignment of video signals of arbitrary relative frequency.
2. Related Art
The phase locking of one signal to another signal is required in many areas of electrical design. Typically, such signal synchronization is accomplished through the use of phase lock loop technology, where the frequency of one signal is periodically adjusted to remain synchronized to a reference frequency. In video applications, it may be desirable to synchronize video from two different sources. For example, one may wish to align two video signals of HDTV (High Definition Television) format, with frame-by-frame, line-by-line, or even pixel-by-pixel synchronization. This may be useful for viewing images in a head-mounted display, with the separate sources respectively providing the left eye and right eye video. To suitably align the two separately sourced video signals, one of them must be monitored and periodically adjusted to maintain synchronization with the other.
In video applications, there are specific signal format considerations to take into account when determining how to synchronize signals. A pixel clock is commonly used to clock out pixel-by-pixel video information. The pixel clock is usually not transmitted with the video. Instead, pulses are incorporated into the video signal indicating the start of each horizontal scan line. This pulse is called Hsync (horizontal sync). The period of this horizontal sync pulse is divided by some integer to recover the pixel clock. A number of different video formats exist, including NTSC, which has 525 horizontal lines per vertical frame, and HDTV, which has 1,250 lines per frame. These video formats have a line ratio of 50:21. To synchronize these formats using traditional techniques, the HDTV clock would be adjusted at best every 50 lines (or 21 lines of the NTSC signal).
When synchronizing local video to video from external sources, phase locking techniques are frequently used. The external Hsync signal is typically separated from the composite video signal, and compared with the Hsync signal from the local video timing generator. The difference in arrival time of these two Hsync pulses is proportional to the phase error, and the sign of the difference is an indication of the lead/lag relationship between local and external Hsync signals. This error value is used to increase or retard the frequency of the local pixel clock generator until the local video timing generator is locked to external video with zero phase error. This means that corresponding pixels in local and external video scan lines match in time. Once horizontal lock is achieved, vertical lock is achieved by simply resetting the vertical line counter of the local video timing generator.
Although the above examples illustrate how video formats with the same frame rate can be synchronized, the frame rate restriction need not hold, and the signals need not be video signals. One such example is in the operation of a rate converter, a common product in the video industry. Film is recorded at 24 frames per second, while video is recorded at 30 frames per second. When transferring the film to video, the data conversion must be done with accurate clocking. Traditional synchronization techniques allow clock correction at every 5 frames of the film, which is equal to 6 frames of the video. It would be advantageous if clock correction could occur at a more frequent rate than the 6:5 field rate would allow. Similar problems arise when converting American NTSC (60 Hz) video to European PAL (50 Hz) video.
Other areas of non-video signal application include the tight phase control of clock signals. For example, a system may require asynchronous clocking, and also require that the two clocks be out of phase alignment. Traditional technology requires that the clocks first be synchronized, and the phase then be adjusted using other techniques. It would be advantageous if the clock could be synthesized with the correct phase by design. This could result in significantly simpler board designs.
Phase lock loop technology is commonly used to synchronize external and local Hsync signals. The synchronization of two video signals may also be referred to as Genlock. Genlock essentially relates to the phase locking of two signals with active feedback through the use of a phase-locked loop.
FIG. 1 illustrates a conventional phase lock loop 100, in which phase locking of two signals, an external signal 116 and a local signal 110, takes place. Phase lock loop 100 includes a phase difference detector 102, a local clock filter 104, a clock generator 108, and a local signal generator 120.
Phase difference detector 102 determines the phase difference between local signal 110 and external signal 116. External signal 116 is received from an external signal source 106. The phase difference determined is represented by an actual phase difference signal 112. If the value of actual phase difference signal is equal to zero, local signal 110 is locked in phase with external signal 116. If the value of actual phase difference signal 112 is not equal to zero, local signal 110 is not locked in phase with external signal 116, and the frequency of local signal 110 needs to be corrected in order to affect the phase of local signal 110 relative to external signal 116.
Local clock filter 104 receives actual phase difference signal 112, and creates an adjustment signal 105 for clock generator 108. Local clock filter 104 is usually a low-pass filter that removes any jitter in the clocking adjustments, and allows for the smooth alignment of local signal 110 and external signal 116 without ringing.
Clock generator 108 receives adjustment signal 105 and external reference clock 122, and creates a local clock signal 118. Clock generator 108 is frequently a voltage controlled oscillator (NCO) or counter. In the case where clock generator 108 is a voltage controlled oscillator (VCO), adjustment signal 105 is a voltage level. External reference clock 122 is used to provide the center frequency for clock generator 108. This frequency, in conjunction with an m-over-n frequency multiply/divide internal to clock generator 108, sets the overall target frequency of local clock signal 118. This target frequency can be marginally increased or decreased by varying the value of adjustment signal 105.
Local clock signal 118 is then received by local signal generator 120, and used to create local signal 110. Local signal generator 120 can be either an external block of logic, or logic internal to phase lock loop 100. This block generally takes the form of a frequency divider used to create a signal of the same frequency as the external reference.
The approach of FIG. 1 suffers from limitations. Phase lock loop 100 can only synchronize signals of the same frequency. This creates problems when it is desired to synchronize video formats which have different line frequencies. For example, NTSC, with 525 total lines (including vertical blanking period), does not line up line-by-line with HDTV, which consists of 1,250 total lines. With the approach of FIG. 1, the signals may only be aligned once per vertical frame, on the occurrence of the vertical sync signal (Vsync), perhaps 30 or 60 times per second, or with external masking logic on the local and external reference, every 50 HDTV lines or 21 NTSC lines. The viewer may be able to detect visually that the signals are not tightly synchronized. There may be a large amount of signal drift of one signal in relation to the other in between Vsync, or sparse Hsync, signals. When a high degree of accuracy in matching is desired, synchronizing only once per frame may not be adequate.
These limitations arise due to difficulty in simply and accurately measuring an arbitrary phase. The most common type of phase detection uses a charge pump. A charge pump is essentially a capacitor that begins charging when one signal arrives, and is then sampled by the second signal. Providing an accurately varying bias to this type of logic is very difficult. Furthermore, because traditional genlocking clock chips are analog by design, they are very susceptible to noise in the power supply. This sensitivity to noise drives up the costs of board design by requiring strict voltage regulation and noise filtering near the clock synthesis chip. A digital clock chip is more robust. It would be advantageous to incorporate the genlocking features of an analog design in a digital clock chip.
Additionally, when dealing with a variety of video formats, it may be impractical to maintain a separate signal source for each format in the laboratory. For example, a laboratory environment may have an established NTSC xe2x80x9chouse syncxe2x80x9d signal, to which the laboratory equipment is synchronized. A great deal of effort and expense may have been expended in establishing the signal for widespread laboratory use. If the laboratory now desires to also use HDTV equipment, it may need to establish a new HDTV house sync signal. It would be advantageous if instead of establishing a new HDTV house sync signal, the new HDTV equipment could be synchronized to the established NTSC house sync signal.
Briefly stated, the present invention is a system and method for the phase-alignment of signals of arbitrary relative frequency. The invention uses a ratiometric calculator to determine the expected phase difference between the two signals at any time. Knowing the expected phase difference at all times makes possible the phase alignment of the two signals.
The phase alignment loop includes a local phase detector, a ratiometric calculator, a phase comparator, a local clock filter, a clock generator, and a local signal generator. The local phase detector detects a phase difference between a first signal pulse and a corresponding second signal pulse. This phase difference may be non-zero. The phase comparator compares this phase difference to an expected phase difference, calculated by the ratiometric calculator, to produce an error signal proportional to the difference. The local clock filter filters the error signal. The clock generator has the ability to adjust the frequency of a local clock signal by an amount based on the filtered error signal, in order to produce a phase aligned local clock signal. The frequency of the phase aligned local clock signal is divided to produce a first signal which is in phase alignment with the second signal.
In a preferred embodiment of the invention, the phase alignment loop is used to align a synthesized clock signal, such that it has a specific phase relative to an external reference signal. The external reference signal is a video Hsync signal. This external Hsync signal will be synchronized with a local Hsync signal generated by logic from the synthesized clock signal. In video applications, Hsync signals are frequently used to synchronize formats. This phase alignment loop may be used to align signals of a variety of different video formats, including NTSC and HDTV, or virtually any signals of arbitrary relative phase and frequency.
The present invention is directed toward a system and method for phase aligning a first signal and a second signal, wherein the first and second signals have different frequencies. A local phase detector detects a phase difference between a first signal pulse and a corresponding second signal pulse. The local phase detector receives the first signal, which starts a first local counter counting, producing a ramp signal of a frequency equal to the frequency of the first signal, that is locked in phase with the first signal. A second signal pulse is then received. This second signal pulse samples the ramp signal, providing a value which corresponds to the phase difference between the first signal pulse and the corresponding second signal pulse.
The phase comparator compares this detected phase difference to an expected phase difference, producing an error signal proportional to the difference. The phase comparator receives the expected phase difference from a ratiometric calculator. The ratiometric calculator includes a second local counter, which also produces a ramp signal. The value of this second ramp signal at any time corresponds to the expected phase difference between the first and second signals. The second signal pulse samples the second local counter, producing a value proportional to the expected phase difference at the current time. A phase comparator then compares this expected phase difference to the previously detected phase difference.
The clock generator then adjusts the frequency of the first signal by an amount based on this error signal, to phase align the first signal to the second signal. The clock generator receives an external reference clock signal. This external reference clock signal is used to create the first signal by dividing the frequency of the external reference clock signal by a delta value. The error signal is used to adjust the delta value to produce a corrected delta value. The clock generator then divides the frequency of the external reference clock signal by the corrected delta value to adjust the frequency of the first signal. This process phase aligns the first signal with the second signal.
In another aspect, instead of directly adjusting the first signal, the clock generator creates an adjusted local clock signal by dividing the frequency of the external reference clock signal by the corrected delta value. A divide by N counter then divides the frequency of the adjusted local clock signal by N, creating an adjusted first signal, wherein N is equal to the number of local clock signal pulses per first signal pulse.
In a further aspect of the present invention, a system and method for phase aligning a first video signal and a second video signal, wherein the first and second video signals have a common frame rate and different line rates, is provided. A detector detects a phase difference between a pulse of the first video signal and a corresponding pulse of the second video signal. A phase comparator compares the detected phase difference to an expected phase difference to produce an error signal proportional to the difference. A clock generator adjusts the frequency of one of the first and second video signals based on the error signal to phase align the first and second video signals.
In a preferred embodiment, the present invention uses the expected phase comparator to compute the expected phase difference at any time between the local and reference signals. It then compares this expected phase value to the actual phase difference signal received, to produce a phase error signal. In this manner, signals of arbitrary relative frequencies may be phase-aligned. This provides a number of advantages, such as:
(1) It allows accurate Genlock between dissimilar video formats, as long as their vertical rate (frame rate) is the same.
(2) In video applications, when synchronizing dissimilar video formats, the present invention allows synchronization to occur on receipt of every horizontal sync signal of the reference signal. This is an improvement over prior systems, where synchronization only occurred on receipt of the vertical or frame sync signal.
(3) It allows for the use of one xe2x80x9chouse syncxe2x80x9d signal to which equipment of varying video formats can be uniformly synchronized.